BiFAST demonstration @ imec Technology Forum featured on EE Times

The live demonstration of the BiFAST OSFP cable at imec's Technology Forum (ITF) did not go unnoticed, and got featured on EE Times: [article]

BiFAST demonstrates 100 Gb/s OSFP cable at DesignCon 2017 on Amphenol booth

During the DesignCon 2017 exhibition, BiFAST demonstrated a live running 100 Gb/s per channel OSFP cable, displaying the real-time BER measurements.

BiFAST shows 56 Gb/s over Samtec ZRay interposer at DesignCon 2017

The performance of the Samtec ZRay interposer was shown during the DesignCon 2017 exhibition using a BiFAST transmitter IC to generate 56 Gb/s NRZ and displaying the NRZ eye on an oscilloscope.

Xilinx, Keysight and Cisco team up with BiFAST for DesignCon 2017 paper

To fill the void in the industry to model and simulate duobinary signaling, Xilinx, Keysight and Cisco have teamed up with BiFAST to develop an IBIS-AMI model of link systems using duobinary signaling. Furthermore, Keysight published this as a White Paper. [publications]

BiFAST CEO Timothy De Keulenaer receives Nokia Bell Scientific Prize

For his PhD thesis A Duobinary Receiver Chip for 84 Gb/s Serial Data Communication, BiFAST CEO Timothy De Keulenaer was awarded the Nokia Bell Scientific Prize by the FWO/FNRS on November 30th 2016, in recognition of the PhD thesis that brings the most original contribution in the field of information and communication technology.

ECOC2016 Post Deadline Paper enabled by BiFAST

The ECOC 2016 post deadline Paper First Demonstration of Real-Time 100 Gbit/s 3-Level Duobinary Transmission for Optical Interconnects showed the versatility of the BiFAST chipset, using the ICs to set up a 100 Gb/s optical interconnect. The conference paper also resulted in a publication in the Journal of Lightwave Technology, see our [publications].

Why BiFAST?

Responsive

BiFAST aims for a 24h response time on all technical queries to maximize productivity for both parties.

Passion

With high speed IOs being our passion, we follow the latest evolutions and developments on the 100 Gbps, 400 Gbps and beyond.

Lean

Being a small team, BiFAST works with limited overhead and as such is able to offer competitive pricing and fast turn-around times.

5+
Process technologies
10+
Silicon-verified designs
100%
On-time delivery

Meet the BiFAST Founding Team

Timothy De Keulenaer, Ph.D.

CEO

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University where he received his Ph.D. degree in applied electrical engineering in 2015. Timothy has gathered four years of experience in the field of high-speed transceivers and duobinary. He is the author of several papers on high-speed SERDES systems and the co-inventor of three patents.

Arno Vyncke, Ph.D.

COO

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University, his expertise encompasses FPGAs and the integration of VCOs and CDRs ranging from 2.5Gb/s to 40Gb/s. His role within BiFAST mainly involves the exploration of business opportunities, running the day-to-day operations and the development of digital blocks in the next transceiver generation.

Ramses Pierco, Ph.D.

VP of Engineering

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University where he received his Ph.D. degree in applied electrical engineering in 2015. He is responsible for the technology development within BiFAST and is leading the ASIC design team.

Renato Vaernewyck

Senior Engineer

Graduated in 2010 as a Master of Science in applied electrical engineering at Ghent University where he received his Ph.D. degree in applied electrical engineering in 2014. He has extensive experience in the design of low-power, high-speed driver circuits for optical modulators and VCSELs. He leads the R&D and testing efforts within BiFAST..

Demonstrators

Over the years BiFAST has worked together with various partners to bring live demonstrations of their chipset's capabilities.

100 Gb/s OSFP cable in collaboration with Amphenol

,DesignCon 2017, Santa Clara, USA, Jan 2017

In collaboration with Amphenol, BiFAST showed single-lane 100 Gb/s communication running live over a 1m OSFP cable built with Amphenol SpectraStrip TwinAx during DesignCon 2017 at the Amphenol booth.

56 Gb/s ZRay interposer in collaboration with Samtec

DesignCon 2017, Santa Clara, USA, Jan 2017

Using the BiFAST transceiver, 56 Gb/s NRZ transmission was demonstrated across a Samtec ZRay interposer showing live NRZ eye diagrams at the Samtec booth during DesignCon 2017. This demonstration was based on the transmitter board that is available for evaluation.

56 Gb/s Backplane and 100 Gb/s Twinax in collaboration with Amphenol

DesignCon 2016, Santa Clara, USA, Jan 2016

At DesignCon 2016 a new standard in high serial data rates was set by achieving 100Gb/s across a 1.5 m twinaxial 26AWG cable (highest serial data rate ever shown across copper). Furthermore the performance of our current duobinary chipset was confirmed by achieving 56 Gb/s across a 20 inch backplane channel.

56 Gb/s Backplane in collaboration with FCI

DesignCon 2015, Santa Clara, USA, Jan 2015

The DesignCon 2015 demonstrator showed the superior performance of duobinary on high loss channels by achieving 56 Gb/s over a backplane with 35 dB loss at Nyquist (28 GHz).

PUBLICATIONS

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